Getting EUV Ready for 2020

Imec, the world-leading research and innovation hub in nanoelectronics and digital technology, continues to advance the readiness of EUV lithography with particular focus on EUV single exposure of Logic N5 metal layers, and of aggressive dense hole arrays. Imec's approach to enable EUV single patterning at these dimensions is based on the co-optimization of various lithography enablers, including materials, metrology, design rules, post processing and a fundamental understanding of critical EUV processes. The results, that will be presented in multiple papers at this week's 2018 SPIE Advanced Lithography Conference, are aimed at significantly impacting the technology roadmap and wafer cost of near-term technology nodes for logic and memory.

Getting EUV Ready for 2020

Fixes to chemistry and design needed to extend lithography cost savings, according to Imec analysis

Thu 1 Mar 18 from IEEE Spectrum

Imec pushes the limits of EUV lithography single exposure

Imec, the world-leading research and innovation hub in nanoelectronics and digital technology, continues to advance the readiness of EUV lithography with particular focus on EUV single exposure ...

Mon 26 Feb 18 from Phys.org

EUV Integration at 5nm Still Risky, With Major Problems to Solve

TSMC, GlobalFoundries, Samsung, and Intel are all integrating EUV at future process nodes, even though major research firms are warning about high defect densities and other problems. Why the ...

Tue 6 Mar 18 from Extremetech

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